1. Field of the Invention
The present invention relates to interrupt control apparatus and methods, particularly to interrupt control apparatus having a break-interrupt function of interrupting execution of a program in a so-called debugger, i.e., a system for supporting debug of a program.
2. Description of the Related Art
Conventionally, high-performance processors have been used in the fields of supercomputers, general-purpose computers, and workstations. In addition, recently, high-performance processors are also used in the field of built-in devices because the required processing capability increases. Such a processor has an interrupt processing function. When an interrupt occurs, the processor performs interrupt processing in accordance with an instruction of an interrupt handler, which is an interrupt processing program.
When a processor is used in the field of supercomputers, general-purpose computers, or workstations, the interrupt handler is generally provided as part of the system program.
Contrastingly when a processor is used in the field of built-in devices, the user often generates his own interrupt handler as part of an application program. Hence, when this interrupt handler is generated, not only the application program but also the interrupt handler itself is subjected to debug.
A processor has various interrupt functions such as an instruction breakpoint, a data breakpoint, a software breakpoint, and step execution as effective functions of supporting debug of a program. Interrupts by the instruction breakpoint, data breakpoint, software breakpoint, and step execution will be totally called a “break-interrupt”, and an interrupt other than the break-interrupt will be called a “normal interrupt”, thereby discriminating them from each other.
An interrupt by an instruction breakpoint occurs when the address (instruction break address) of an instruction to be interrupted is set in a register, and the instruction break address set in this register matches the instruction address of an actually executed instruction. An interrupt by a data breakpoint occurs when the address (data break address) of data to be interrupted is set in a register, and the data break address set in this register matches the address of data accessed in accordance with a load instruction or store instruction.
An interrupt by a software breakpoint occurs when a breakpoint instruction for generating an interrupt is inserted to an arbitrary position in a program, and the breakpoint instruction is executed when the program is being sequentially executed in accordance with the progress of a program counter. An interrupt by step execution occurs every time one instruction of a program is executed.
By using the above-described break-interrupt function, execution of a program is interrupted to confirm repeatedly calculation results stored in a register or memory, thereby debugging the program.
FIG. 1 is a representation showing an example of state transition when a processor interrupt occurs.
Referring to FIG. 1, reference numeral 301 denotes a user state (normal operative state without any interrupt) of the processor; and 302 denotes a supervisor state (privilege instruction execution state by an interrupt) of the processor. When the processor is processing a normal application, the state of the processor is the user state 301. When an interrupt 303, i.e., a break-interrupt or normal interrupt occurs in the user state 301, the processor transits to the supervisor state 302. When an interrupt return instruction 304 is executed in this supervisor state 302, the processor returns to the user state 301.
FIG. 2 is a representation showing another example of state transition when a processor interrupt occurs.
Referring to FIG. 2, reference numeral 311 denotes a user state of the processor; and 312, 313, and 314 denote supervisor states of the processor. When the processor is processing a normal application, the state of the processor is the user state 311. When an interrupt 315, i.e., a break-interrupt or normal interrupt occurs in the user state 311, the processor transits to the supervisor state 312.
When an interrupt return instruction 316 is executed in the supervisor state 312, the processor returns to the user state 311. However, when an interrupt 317, i.e., a break-interrupt or normal interrupt occurs in the supervisor state 312 before execution of the interrupt return instruction 316, the processor transits to another supervisor state 313. When an interrupt return instruction 318 is executed in the supervisor state 313, the processor returns to the previous supervisor state 312.
Interrupt processing control will be described below with reference to FIG. 2 by exemplifying processor state transition: user state 311→supervisor state 312→user state 311 due to an interrupt.
When the interrupt 315, i.e., a break-interrupt or normal interrupt occurs in the user state 311, the processor writes, in a register, information on program counter value, processor state, and factor of the interrupt at the time of interrupt, thereby saving the processor operation information before the interrupt. The processor transits to the supervisor state 312 and shifts processing from the application program to an interrupt handler.
Immediately after the shift to processing of the interrupt handler, i.e., immediately after the interrupt processing, rewrite in the register in which the program counter value, the processor state, and the factor of the interrupt are written is inhibited, thereby inhibiting a new interrupt. When the interrupt processing progresses to some extent, rewrite in the register in which the program counter value, the processor state, and the factor of the interrupt are written is permitted, thereby permitting a new interrupt (e.g., the interrupt 317).
When processing of the interrupt handler is almost ended, and the interrupt return instruction 316 is executed in the supervisor state 312, the processor returns to the user state 311 before the interrupt. At this time, the processor operation information before the interrupt is restored on the basis of the information on program counter value and processor state which are written in the register before the interrupt, thereby returning the processor to the user state 311 before the interrupt.
Immediately before this interrupt return as well, write in the register is inhibited, thereby inhibiting a new interrupt. When interrupt return of the processor is ended, rewrite in the register in which the program counter value, the processor state, and the factor of the interrupt are written is permitted, thereby permitting a new interrupt.
As described above, in the conventional interrupt control apparatus, when an interrupt occurs, a write in the register used to write the processor operation information is inhibited immediately after the interrupt operation and immediately before interrupt return. For this reason, interrupt inhibition periods when a new interrupt is inhibited are present immediately after the interrupt operation and immediately before interrupt return. In addition, the processor writes the processing operation information before the interrupt in the same register without discriminating a break-interrupt from a normal interrupt. Hence, immediately after a normal interrupt occurs or immediately before its return, no break-interrupt can occur because of the presence of interrupt inhibition periods. For this reason, the interrupt handler cannot be completely debugged.
Many conventional debug support systems have a break-interrupt function of interrupting execution of a program to verify the operation of the program. The break-interrupt function occasionally stops execution of a program at an arbitrary position designated in advance in the program to be debugged. This function is effective for program debug processing and incorporated in many debug support systems.
This break-interrupt function can be implemented by various schemes including a breakpoint function of stopping execution of a program at a predetermined instruction. To use this function, the user designates in advance an instruction at which execution is to be stopped and then starts the program to be debugged. Thus, the program to be debugged stops its execution with the designated instruction. The user can check or change the value of a register or memory at the time of stop, as needed. After that, execution of the program can be resumed from the time of stop.
To implement this breakpoint function, for example, an instruction breakpoint or software breakpoint can be used.
An interrupt by an instruction breakpoint occurs when the address (instruction break address) of an instruction to be interrupted is set in a register, and the instruction break address set in this register matches the instruction address of an actually executed instruction.
More specifically, for this instruction break, a breakpoint register for holding the address of an instruction at which execution is to be stopped is prepared as hardware. When the instruction designated by this register is detected during normal processing of an application program, a normal interrupt occurs, the control is shifted to the debug support program through an interrupt processing program such as a so-called interrupt handler, and the user is notified of it. After that, when debug by the user is completed, and resumption of the original program is instructed, the control is returned to the original application program.
An interrupt by a software breakpoint occurs when an instruction designated at an arbitrary position in a program is replaced with an instruction for generating an interrupt, and the instruction for generating an interrupt is executed while the program is sequentially executed in accordance with the progress of the program counter. As the instruction for generating an interrupt, a dedicated instruction called a breakpoint instruction may be prepared.
More specifically, when an instruction for generating an interrupt is detected during normal processing of an application program, a break-interrupt occurs, the control is shifted to the debug support program through an interrupt processing program such as a so-called interrupt handler, and the user is notified of it. After that, when debug by the user is completed, and resumption of the original program is instructed, execution of the replaced original instruction is simulated, and then, the control is returned to the original application program.
The scheme using an instruction breakpoint has the following characteristic features.                The program to be debugged need not be changed.        Execution of the instruction need not be simulated.        The number of settable breakpoints is substantially limited because of limitations on hardware such as a register.        
As a characteristic feature of the scheme using a software breakpoint,                a number of breakpoints can be set in a program.        
FIG. 3 is a block diagram showing a conventional construction for implementing the instruction break scheme by a hardware mechanism.
Referring to FIG. 3, reference numeral 10 denotes a memory which stores programs including an application and an interrupt handler; 20 denotes an instruction fetch section; 30 denotes an instruction execution section; 40 denotes an interrupt control section; and 50 denotes a register section.
The instruction fetch section 20 comprises a program counter (PC) 21 for indicating the address of an instruction word to be read out from the memory 10, an instruction register (IR) 22 for holding the instruction word read out from the memory 10, and an instruction break detection section 23. The instruction fetch section 20 reads out an instruction word 62 from the memory 10 on the basis of an instruction address 61 indicated by the program counter 21 and writes/holds the read-out instruction word 62 in the instruction register 22. The instruction fetch section 20 also supplies an instruction word 63 held in the instruction register 22 to the instruction execution section 30.
When an instruction address 64 of a branch destination or an instruction address 65 for return from the interrupt state is supplied from the instruction execution section 30, or when an instruction address 66 of the interrupt handler is supplied from the interrupt control section 40, the instruction fetch section 20 writes the received instruction address in the program counter 21. Otherwise, the value of the program counter 21 is incremented by one sequentially to read out the next instruction word.
The instruction break detection section 23 comprises breakpoint registers 24-0 to 24-n, determination sections 25-0 to 25-n, provided in accordance with the registers, respectively, and an OR circuit 26 for ORing determination results from the determination sections 25-0 to 25-n.
Each of the breakpoint registers 24-0 to 24-n has an address register 24a for holding the address of a breakpoint at which execution is to be stopped, and a flag register 24b representing whether the instruction break operation is valid. The flag register 24b having a value “1” means an instruction break operation valid state, and the flag register 24b having a value “0” means an instruction break operation invalid state.
Each of the determination sections 25-0 to 25-n, determines whether the generation condition for an instruction break held in the corresponding one of the breakpoint registers 24-0, to 24-n, is satisfied. More specifically, each of the determination sections 25-0 to 25-n, compares the instruction break address held in the address register 24a of the corresponding one of the breakpoint registers 24-0 to 24-n, with the current execution address supplied from the program counter 21, thereby determining whether the two addresses match.
If the two addresses match, and the value of the flag register 24b is “1”, it is determined that the instruction break generation condition is satisfied. On the other hand, if the two addresses do not match, or the value of the flag register 24b is “0” though the two addresses match, it is determined that the instruction break generation condition is not satisfied. The determination sections 25-0 to 25-n supply determination signals representing the determination results to the OR circuit 26.
The OR circuit 26 performs OR operation to the determination signals supplied from all the determination sections 25-0 to 25-n. When the instruction break generation condition is satisfied for at least one determination section, the OR circuit 26 detects a break-interrupt by an instruction breakpoint and notifies the interrupt control section 40 of the break-interrupt using an interrupt notification signal 67.
The instruction execution section 30 executes processing such as calculation, branch, data load/store, or return from the interrupt state in accordance with the instruction of the instruction word 63 supplied from the instruction fetch section 20. For example, if the supplied instruction is a calculation instruction, the instruction execution section 30 executes calculation on the basis of a data value 69 read out from a general-purpose register (GR) 55 in the register section 50, which is designated by a register address 68, and writes a data value 70 obtained by this calculation in the general-purpose register 55 designated by the register address 68.
If the supplied instruction is a branch instruction, and the branch condition is satisfied, the instruction execution section 30 supplies the instruction address 64 of the branch destination to the instruction fetch section 20. If the supplied instruction is a load instruction, the instruction execution section 30 obtains the effective address on the memory 10 from the data value 69 read out from the general-purpose register 55 designated by the register address 68, reads out read data 71 from an area of the memory 10, which corresponds to the effective address, and writes the read-out data in the general-purpose register 55 designated by the register address 68.
When the supplied instruction is a store instruction, the instruction execution section 30 obtains the effective address on the memory 10 from the data value 69 read out from the general-purpose register 55 designated by the register address 68, and writes the data value 69 read out from the general-purpose register 55 designated by the register address 68 in an area of the memory 10, which corresponds to the effective address.
When the supplied instruction is an instruction for return from the interrupt state, the instruction execution section 30 executes the return operation from the interrupt state. More specifically, on the basis of operation information before the interrupt, which is held in each register of the register section 50, processing of restoring the operation information before the interrupt is executed.
In this case, the value of a previous state register (EPSR) 53 is written in a present state register (PSR) 54, and simultaneously, the value of a return address register (EPCR) 52 is read out, and the read-out return address is supplied to the instruction fetch section 20 as the branch destination address 65.
When an interrupt due to an error such as division by zero or data overflow is detected in executing a calculation instruction by the instruction execution section 30, the instruction execution section 30 notifies the interrupt control section 40 of the interrupt using an interrupt notification signal 74. The interrupt due to an error is called a normal interrupt and discriminated from a break-interrupt by an instruction break or software break.
When receiving the interrupt notification signal 67 for a break-interrupt from the instruction fetch section 20, or the interrupt notification signal 74 for a normal interrupt from the instruction execution section 30, the interrupt control section 40 controls the instruction fetch section 20 and the register section 50 to execute the shift operation to the interrupt state.
More specifically, when receiving the interrupt notification signal 67 or 74, the interrupt control section 40 reads out an instruction address 73 at the time of interrupt from the program counter 21 of the instruction fetch section 20 and writes the instruction address 73 in the return address register 52 of the register section 50. The start address 66 of the interrupt handler corresponding to the interrupt that has occurred is supplied to the instruction fetch section 20 and set in the program counter 21. The interrupt control section 40 also writes the processor state before the interrupt in the previous state register 53 and writes, in the present state register 54, the processor state that has transited in accordance with the interrupt.
The register section 50 has a condition register 51 in addition to the above-described return address register 52, previous state register 53, present state register 54, and general-purpose register 55. This condition register 51 holds a condition code that is referred to when the instruction execution section 30 executes a conditional instruction, which is supplied from the instruction fetch section 20. A conditional instruction means an instruction for which it is determined first whether a designated condition is satisfied, and only when the condition is satisfied, designated processing such as data transfer or calculation is executed.
The return address register 52 holds the original instruction address (the value 73 of the program counter 21 at the time of interrupt) to which the processor will return from the interrupt state. The previous state register 53 holds the processor state (normal user state without any interrupt or supervisor state that has transited in accordance with the interrupt) before the interrupt. The present state register 54 holds the present processor state.
The state transition of the processor will be briefly described.
When the processor is processing a normal application program, the processor state is the user state. When an interrupt occurs in this user state, the processor transits to the supervisor state. When an interrupt return instruction is executed in this supervisor state, the processor returns to the user state.
On the other hand, if another interrupt occurs before the interrupt return instruction is executed in the supervisor state, the processor transits from the current supervisor state to the next supervisor state. When the interrupt return instruction is executed in this new supervisor state, the processor returns to the previous supervisor state.
The operation of the processor shown in FIG. 3 will be described next. When the processor is in the user state, the instruction fetch section 20 reads out the instruction word 62 from the memory 10 on the basis of the instruction address 61 indicated by the program counter 21, and writes/holds the read-out instruction word in the instruction register 22. The instruction fetch section 20 also supplies the instruction word 63 held in the instruction register 22 to the instruction execution section 30.
The instruction execution section 30 decodes the instruction word 63 supplied from the instruction fetch section 20 and executes processing of the supplied instruction in accordance with the decoding result. If no break-interrupt or normal interrupt occurs in this user state, the processor repeats the above operation.
However, when the instruction fetch section 20 detects a break-interrupt, the instruction fetch section 20 notifies the interrupt control section 40 of the break-interrupt using the interrupt notification signal 67. When the instruction execution section 30 detects a normal interrupt, the instruction execution section 30 notifies the interrupt control section 40 of the normal interrupt using the interrupt notification signal 74.
When receiving the interrupt notification from the instruction fetch section 20 or instruction execution section 30, the interrupt control section 40 controls the instruction fetch section 20 and register section 50 to perform processing as follows.
First, the interrupt control section 40 reads out the currently indicated instruction address 73 from the program counter 21 and writes the read-out instruction address 73 in the return address register 52.
The interrupt control section 40 also reads out the processor state (user state) before the interrupt from the present state register 54, writes the read-out processor state in the previous state register 53 and, also writes, in the present state register 54, the processor state that has transited in accordance with the interrupt. Thus, the processor transits from the user state to the supervisor state. The interrupt control section 40 also supplies the start address 66 of the interrupt handler corresponding to the interrupt to the instruction fetch section 20 and sets the address value in the program counter 21.
The processor which has transited to the supervisor state reads out the instruction word 62 of the interrupt handler to the instruction fetch section 20 in accordance with the start address 66 of the interrupt handler, which is set in the program counter 21, temporarily holds the read-out instruction word in the instruction register 22, and then supplies the instruction word to the instruction execution section 30.
The instruction execution section 30 decodes the supplied instruction word 63 and executes processing in accordance with the decoding result. At this time, the instruction execution section 30 repeats the operation of executing the instruction word 63 sequentially supplied toward the end address of the interrupt handler. When processing of the interrupt handler corresponding to the interrupt is ended, the processor executes the interrupt return instruction.
When receiving the interrupt return instruction, the instruction execution section 30 reads out the value of the previous state register 53 and writes the value in the present state register 54. Thus, the processor transits from the supervisor state to the user state. The instruction execution section 30 also reads out the original instruction address to which the processor will return from the interrupt state from the return address register 52, supplies the instruction address to the instruction fetch section 20 as the branch destination address 65, and sets the instruction address in the program counter 21.
On the basis of the original instruction address 61 set in the program counter 21, the instruction fetch section 20 reads out the instruction word 62 for the normal operation from the memory 10, temporarily holds the instruction word 62 in the instruction register 22, and then supplies the instruction word to the instruction execution section 30. The instruction execution section 30 executes processing of the remaining part of the application program corresponding to the normal operation.
To set execution of a break-interrupt by an instruction break, for an entry of interest in entries #0 to #n corresponding to the breakpoint registers 24-0 to 24-n in the instruction break detection section 23, the target address of a breakpoint is written in the address register 24a, and the value “1” representing the instruction break operation valid state is written in the flag register 24b. 
To cancel execution of the break-interrupt by an instruction break, for an entry of interest in the entries #0 to #n corresponding to the breakpoint registers 24-0 to 24-n, in the instruction break detection section 23, the value “0” representing the instruction break operation invalid state is written in the flag register 24b. 
FIG. 4 is a block diagram showing a conventional construction for implementing the software break scheme by a breakpoint instruction.
In FIG. 4, the same reference numerals as in FIG. 3 denote the same functional parts as in FIG. 3, respectively, and a detailed description thereof will be omitted.
Referring to FIG. 4, when detecting a normal interrupt due to an instruction address conversion error or the like, an instruction fetch section 20 notifies an interrupt control section 40 of the normal interrupt using an interrupt notification signal 81.
When a breakpoint instruction is supplied in executing an instruction supplied from the instruction fetch section 20 by an instruction execution section 30, the instruction execution section 30 notifies the interrupt control section 40 of the software break-interrupt using an interrupt notification signal 82.
FIG. 5 is a representation showing the construction of a breakpoint table held by the instruction execution section 30 in the software break scheme.
Referring to FIG. 5, a column “VALID” represents whether the breakpoint operation is valid. A value “1” means a breakpoint operation valid state while a value “0” means a breakpoint operation invalid state.
A column “ADDRESS” holds the target address of a breakpoint at which execution is to be stopped. A column “INSTRUCTION” holds a breakpoint target instruction word. The breakpoint target instruction word is replaced with a breakpoint instruction for generating a break-interrupt. For this reason, in canceling the breakpoint operation, restoration is done using the data of the breakpoint target instruction word held in the column “INSTRUCTION”.
To set execution of a break-interrupt by a breakpoint instruction, for an entry of interest in entries #0 to #n of the breakpoint table shown in FIG. 5, an instruction address representing a breakpoint is written in the column “ADDRESS”, a breakpoint target instruction word is written in the column “INSTRUCTION”, and the value “1 ” representing the breakpoint operation valid state is written in the column “VALID”. In addition, the breakpoint target instruction word is replaced with a breakpoint instruction for generating a break-interrupt.
Contrastingly, to cancel execution of the break-interrupt by a breakpoint instruction, for an entry of interest in the entries #0 to #n of the breakpoint table shown in FIG. 5, the breakpoint target instruction word written in the column “INSTRUCTION” is read out and replaced with a breakpoint instruction. In addition, for the entry of interest, the value “0 ” representing the breakpoint operation invalid state is written in the column “VALID”.
Recent processors are required to make the branch instruction use frequency low in order to improve the processing performance. For this purpose, techniques including a conditional instruction or predicated execution have been proposed (“HPL PlayDoh Architecture Specification ver. 1.0, “Vinod Kathail Etc HPL 93-80 February 1994,” Incorporating Guarded Execution into Existing Instruction Set” D. N. Pnevmatikatos PDH Paper Wisconsin Univ. 1996, and “The Benefit of Predicated Execution for Software Pipelining” N.J. Warter etc. IIICSS-26 Conference Proceedings January 1993 Vol. 1, pp. 497-606).
However, in the conventional interrupt scheme using an instruction break, as shown in FIG. 3, a break-interrupt always occurs when the instruction break generation condition set in each of the breakpoint registers 24-0 to 24-n of the instruction break detection section 23 is satisfied. For this reason, in debugging a program containing a conditional instruction, execution of the program is interrupted when the instruction break generation condition is satisfied while the condition of the conditional instruction is not satisfied.
In the conventional interrupt scheme using a breakpoint instruction, as shown in FIG. 4, a break-interrupt always occurs when a breakpoint instruction that has been replaced in advance is supplied. For this reason, in debugging a program containing a conditional instruction, execution of the program is interrupted when the breakpoint instruction is supplied while the condition of the conditional instruction is not satisfied.